Multiple-output dc-dc converter

ABSTRACT

The multiple-output DC-DC converter comprises an inductor (L) and a main switch (S 0 ) which periodically couples a DC-input voltage (Vin) to the inductor (L). Each one of a multitude of loads (L 1,  L 2 ,L 3 ) is coupled to the inductor (L) via one of a multitude of output switches (S 1,  S 2,  S 3 ). One of a multitude of output voltages (V 1,  V 2,  V 3 ) is present across each of the loads (L 1,  L 02 ,L 3 ). A controller (CO) controls the main switch (S 0 ) and the output switches (S 1,  S 2,  S 3 ) in sequences (SE) of cycles (CY). Each one of the cycles (CY 1,  CY 2,  CY 3 ) contains an on-phase of the main switch (S 0 ) followed by an on-phase of one of the multitude of output switches (S 1,  S 2,  S 3 ). The cycles (CY 1,  CY 2,  CY 3 ) have either a predetermined first (minimum) duty cycle (D 1 ) or a second (maximum) duty cycle (D 2 ) which is larger than the first duty cycle (D 1 ). The controller (CO) comprises a multitude of comparators ( 10, 11, 12 ) which each compare one of the multitude of output voltages (V 1,  V 2,  V 3 ) with an associated one of a multitude of reference voltages (VR 1,  VR 2,  VR 3 ). The controller (CO) further checks whether the number of the multitude of output voltages (V 1,  V 2,  V 3 ) which have a value above their associated reference voltage (VR 1,  VR 2,  VR 3 ) is larger than, smaller than, or equal to the number of the multitude of output voltages (V 1,  V 2,  V 3 ) which have a value below their associated reference voltage (VR 1,  VR 2,  VR 3 ). The duty cycles are selected such that the number of cycles (CY 1,  CY 2,  CY 3 ) with the minimal duty cycle (D 1 ) are larger than, smaller than, or equal to the number of cycles with the maximum duty cycle (D 2 ), respectively.

The invention relates to a multiple-output DC-DC converter, anelectronic apparatus comprising such a multiple-output DC-DC converter,and a method of controlling a multiple-output DC-DC converter.

WO 02/058220-A1 discloses a single output DC-DC converter in which amain switch periodically couples a DC input voltage to an inductor tostore energy in the inductor during an on-period of the main switch.During an off-period of the main switch, a secondary switch couples aload to the inductor to transfer energy from the inductor to the load. Asubsequent on and off-period of the main switch is called a switchingcycle or a cycle. A ratio of the on-period to the duration of a cycle iscalled the duty cycle.

The output voltage of the DC-DC converter is regulated by comparing theoutput voltage across the load with a reference level. If the outputvoltage is above the reference level, this indicates that the amount ofenergy supplied to the load is too high. During the next cycle, the dutycycle will have a predetermined minimum value so that the amount ofenergy stored in the inductor will be minimal. If the output voltage isbelow the reference level, during the next cycle, the duty cycle willhave a predetermined maximum value. The output voltage is thus regulatedby using the minimum and the maximum duty cycle only.

This prior art DC-DC converter is unsuitable for providing multipleindividually regulated output voltages.

It is an object of the invention to provide a multiple-output DC-DCconverter in which the multiple output voltages are each regulated.

A first aspect of the invention provides a multiple-output DC-DCconverter as claimed in claim 1. A second aspect of the inventionprovides an electronic apparatus comprising such a multiple-output DC-DCconverter as claimed in claim 16. A third aspect of the inventionprovides a method of controlling a multiple-output DC-DC converter asclaimed in claim 17. Advantageous embodiments are defined in thedependent claims.

The multiple-output DC-DC converter in accordance with the inventioncomprises an inductor and a main switch which periodically couples aDC-input voltage to the inductor. During the on-time of the main switch,energy is stored in the inductor. Each one of a multitude of loads iscoupled via one of a multitude of output switches to the inductor.Across each of the loads, one of a multitude of output voltages ispresent.

A controller controls the main switch and the output switches insequences of cycles. Each one of the cycles contains an on-phase of themain switch followed by an on-phase of one of the multitude of outputswitches. The cycles have either a predetermined first or a second dutycycle which is larger than the first duty cycle. No other duty cyclesoccur. The first duty cycle is also referred to as the minimum dutycycle, and the second duty cycle is also referred to as the maximum dutycycle.

The controller comprises a multitude of comparators which each compareone of the multitude of output voltages with an associated one of amultitude of reference voltages. The controller further checks whetherthe number of the multitude of output voltages which have a value abovetheir associated reference voltage, is larger than, smaller than, orequal to the number of the multitude of output voltages which have avalue below their associated reference voltage. Depending on the outcomeof the check made by the controller, the duty cycles are selected suchthat the number of cycles with the minimal duty cycle (this number ofduty cycles is further referred to as the first number) are larger than,smaller than, or equal to the number of cycles with the maximum dutycycle (this number of duty cycles is further referred to as the secondnumber), respectively.

In this manner, the total energy stored in the inductor will track thetotal energy required by the loads. For example, if in a DC-DC converterwith three outputs, one of the output voltages is above its associatedreference voltage (also referred to as reference level, or referencevalue), and two of the output voltages are below their associatedreference level, the energy to be supplied to the first mentioned outputshould decrease while the energy supplied to the last mentioned outputshould be increased. Consequently, the total energy stored in theinductor should increase and the number of outputs which require moreenergy is larger than the number of outputs which require less energy.Thus, in the next sequence of cycles, the number of cycles with themaximum duty cycle should be larger than the number of cycles with theminimum duty cycle.

WO 02/058220-A1 discloses a multiple-output DC-DC converter in which theoutputs are independently controlled in either the pulse widthmodulation (further referred to as PWM mode or the pulse frequencymodulation (further referred to as PFM) mode. In the PWM mode, the dutycycles of the outputs differ because for each output the ratio betweenthe input voltage and the output voltage is different. Moreover, theduty cycle is also related the current in the coil of the converter andthe total output power provided. Further, the output has to bedetermined that requires the highest amount of energy. This output hasto operate in the PWM mode. Then, the number of switching cycles of anyother output operating in the PWM mode is determined from which part ofthe total amount of energy has to be supplied to a particular output.This prior art DC-DC converter is complex because it has to bedetermined which output requires the highest amount of energy to controlits duty cycle such that sufficient energy will be stored in theinductor, what the duty cycle of the other outputs should be, and howmany switching cycles have to be applied for a particular output in thetotal switching sequence.

The DC-DC converter in accordance with the invention only has to selecthow many of the two predetermined duty cycles (the minimum and themaximum duty cycle) have to be provided in the total switching sequence.

In an embodiment as defined in claim 2, the number of cycles in asequence to which the minimum duty cycle is allocated, equals the numberof output voltages which have a value above their associated referencevoltage. The number of output voltages which have a value equal to theirassociated reference voltage, are either neglected, or are arbitrarilyassigned to the cycles with the minimum or maximum duty cycle. Thenumber of cycles in the sequence to which the maximum duty cycle isallocated equals the number of output voltages that have a value belowtheir associated reference voltage.

In an embodiment as defined in claim 3, as much as possible with thepresent values of the first number and the second number, one of thecycles with the maximum duty cycle precedes one of the cycles with theminimum duty cycle. In this manner, first, during the cycles with themaximum duty cycle, the average current through the inductor increases,and then, during the cycles with the minimum duty cycle, the averagecurrent through the inductor decreases. Consequently, the chance thatthe current through the inductor becomes zero is minimized.

In an embodiment as defined in claim 4, the order of the cycles in asequence is selected to first comprise all the cycles with the maximumduty cycle and then all the cycles with the minimum duty cycle. Due tothe cycles with the maximum duty cycle, first the average value of thecurrent through the inductor increases, then, due the cycles with theminimum duty cycle, the average value decreases. Again, the chance thatthe current through the inductor becomes zero is minimized.

In an embodiment as defined in claim 5, the minimum duty cycles areallocated as much as possible to cycles of which the correspondingoutput voltages have a value below their associated reference voltage.In cycles with the minimum duty cycle, the duration of the on-time ofthe output switch is larger than in the cycles with the second dutycycle and thus the amount of energy supplied to the associated load islarger. This is exactly what is required at an output with an outputvoltage below its reference value. Similarly, the maximum duty cyclesare allocated as much as possible to cycles of which the correspondingoutput voltages have a value above their associated reference voltage.

Both the number of the minimum and the maximum duty cycles in a sequenceare determined by the number of output voltages above and below theirassociated reference voltages, respectively. Whereas in contrast, theminimum duty cycles are preferably allocated to output switchescorresponding to outputs that have an output voltage below theirreference value and the maximum duty cycles are preferably allocated tooutput switches corresponding to outputs that have an output voltageabove their reference value. Usually, there will be no match in thenumbers concerned, and, consequently, a maximum duty cycle will beallocated to some of the output voltages with a value below theirreference value as defined in claim 7, or a minimum duty cycle will beallocated to some of the output voltages above their reference value, asis defined in claim 6.

In an embodiment as defined in claim 8, in a sequence of cycles, thecycle wherein a lowest amount of energy is transferred is allocated toan output of which the output voltage is above its associated referencevoltage. This causes a minimal further increase of this voltage whichalready has a value higher than its reference value.

In an embodiment as defined in claim 9, the first cycle in a sequence isallocated to an output of which the voltage is above its associatedreference voltage and to which a minimum duty cycle is allocated.Usually, the first cycle in a sequence starts with the lowest averagevalue of the current in the inductor. This is due to the fact thatcycles with the minimum duty cycle occur at the end of the sequence.This lowest amount of energy should be supplied to an output that isgoing to receive a much larger amount of energy than required. This isparticularly true for an output that has already a voltage above itsreference value and to which a minimum duty cycle has to be allocatedbecause there are no maximum duty cycles left.

In an embodiment as defined in claim 10, in a sequence of cycles, thecycle wherein a highest amount of energy is transferred is allocated toan output of which the voltage is below its associated referencevoltage. This causes a minimal further decrease of this voltage whichalready has a value lower than its reference value.

In an embodiment as defined in claim 11, in a sequence, the last cycleto which a maximum duty cycle is allocated is selected to be an outputof which the voltage is below its associated reference voltage and towhich a maximum duty cycle is allocated. Usually, in a sequence, thelast cycle to which a maximum duty cycle is allocated has the highestaverage value of the current in the inductor. This is due to the factthat cycles with the minimum duty cycle occur at the end of thesequence. This highest amount of energy should be supplied to an outputwhich is going to receive a much smaller amount of energy than required.This is particularly true for an output that already has a voltage belowits reference value and to which a maximum duty cycle has to beallocated because there are no minimum duty cycles left.

In an embodiment as defined in claim 12 or 13, if in a particularsequence either the minimum or the maximum duty cycle has to beallocated to an output of which the voltage is above or below itsreference level, respectively, in a next sequence the correct duty cycleis allocated to this output. This has the advantage, that the wrongallocating of duty cycles will be averaged over time and thus itsnegative influence on the regulation of the output voltages concerned isminimized.

In an embodiment as defined in claim 14, the mode of the outputs istracked.

In an embodiment as defined in claim 15, if the mode indicates that anoutput does not need to supply current to the load, no switching cycleshould be allocated to this output to prevent the output voltage to riseeven further.

These and other aspects of the invention are apparent from and will beelucidated with reference to the embodiments described hereinafter.

In the drawings:

FIG. 1 shows a circuit diagram of a prior art single output DC-DCconverter with a dual duty cycle control,

FIG. 2 show signals occurring in the prior art DC-DC converter of FIG.1,

FIG. 3 shows a circuit diagram of a multiple output DC-DC converter inaccordance with an embodiment of the invention,

FIG. 4 show signals for elucidating the DC-DC converter of FIG. 3,

FIG. 5 shows a block diagram of an apparatus with a DC-DC converter inaccordance with the invention,

FIG. 6 shows a state diagram for elucidating the modes of outputvoltages, and

FIG. 7 shows a flow chart of a control algorithm in a DC-DC converter inaccordance with the invention.

Like references in the various Figures refer to like signals or to likeelements performing like function 1.

FIG. 1 shows a circuit diagram of a prior-art single output DC-DCconverter with a dual duty cycle control. The DC-DC converter, which inFIG. 1 is an up-converter 1 comprises a series arrangement of aninductor L and a first switch S1 (the main switch) arranged between afirst input terminal 2 and a second input terminal 3 to receive an inputvoltage Vin. A parallel arrangement of a diode D and a second switch S2(the output switch) is arranged between the junction of the main switchS1 and the inductor L and the first output terminal 4. The second inputterminal 3 and the second output terminal 5 are interconnected. Asmoothing capacitor C is arranged between the first output terminal 4and the second output terminal 5. A load 12 is connected between thefirst output terminal 4 and the second output terminal 5. A comparator 9compares the output voltage Vout at the first output terminal 4 with areference voltage VR at terminal 10 to supply an error signal 11 to thecontroller 6. The controller 6 supplies the control signals 7 and 8 tocontrol the on and off periods of the main switch S1 and the outputswitch S2. The current through the inductor L is indicated by IL. Theoperation of the prior-art DC-DC converter will be elucidated withrespect to FIG. 2.

FIG. 2 show signals occurring in the prior-art DC-DC converter ofFIG. 1. FIG. 2A shows the output voltage Vout and the reference voltageVR, and FIG. 2B shows the current IL through the inductor L.

FIG. 2 show that each cycle CY has two phases. During the first phaseswhich start at the instants t0, t2, t4, t6, t8, the main switch S1 isclosed during the on-time TON while the output switch S2 is open. Duringthe second phases which start at the instants t1, t3, t5, t7, t9,respectively, the main switch S1 is opened during the off-time TOF andthe output switch S2, is closed. During the on-time TON of the mainswitch S1, the current IL in the inductor L increases and energy isstored in the inductor L. During the on-time of the output switch S2,the current IL in the inductor L decreases and energy is supplied to theload 12.

The duty cycle of a cycle CY is defined as the ratio of its on-time TONto the duration of the cycle CY. The DC-DC converter is regulated byselecting the duty cycle out of a first and a second duty cycle, thefirst duty cycle D1 is smaller than the second duty cycle D2. The firstduty cycle D1 is also referred to as the minimum duty cycle, and thesecond duty cycle D2 is further referred to as the maximum duty cycle.

The arrows at the instants t2, t4, t6, t8, t10 indicate sample instantsat which the comparator 9 compares the output voltage Vout with thereference voltage VR. If the output voltage Vout is higher than thereference voltage VR, a succeeding cycle CY will have the minimum dutycycle D1. If the output voltage Vout is lower than the reference voltageVR, a succeeding cycle will have the maximum duty cycle D2.

It is assumed that the value of the capacitor C is sufficiently large tokeep the average level of the output voltage Vout substantiallyconstant. At the instant t2, the main switch S1 is closed and the outputswitch S2 is opened, and consequently, the load 12 will draw a dischargecurrent through the capacitor C which causes a downward jump in thevoltage at the output due to the ESR. The ESR is the series impedance ofthe capacitor C. The linear decrease of the output voltage Vout from theinstant t2 to t3 is due to the load discharging the output capacitor. Atthe instant t3, the main switch S1 is opened and the output switch S2 isclosed: a charge current will flow into the capacitor C. Due to the ESRof the capacitor C, the polarity change of the current will cause anupward jump in the output voltage Vout. The decrease of the outputvoltage Vout from the instant t3 to t4 is due to the coil currentdecrease, resulting in an ESR voltage drop decrease. The comparator 9compares the output voltage Vout with the reference level VR at, or justbefore the instant t4. In the example of FIG. 2, the level of the outputvoltage Vout is below the reference level VR, and thus a maximum dutycycle D2 will be allocated to the next cycle starting at the instant t4.

FIG. 3 shows a circuit diagram of a multiple-output DC-DC converter inaccordance with an embodiment of the invention.

A series arrangement of an inductor L and a main switch S0 is arrangedto receive an input DC-voltage Vin. This input DC-voltage may originatefrom a battery, or may be a rectified mains voltage. The junction of theinductor L and the main switch S0 is denoted by N1. The side of the mainswitch S0, which is not coupled to the node N1, is grounded. A firstoutput switch S1 is arranged between the node N1 and a node O1. A secondoutput switch S2 is arranged between the node N1 and a node O2. A thirdoutput switch S3 is arranged between the node N1 and a node O3. Aparallel arrangement of a first capacitor C1 and a first load L1 iscoupled between the node O1 and ground. A parallel arrangement of asecond capacitor C2 and a second load L2 is coupled between the node O2and ground. A parallel arrangement of a third capacitor C3 and a thirdload L3 is coupled between the node O3 and ground. A first outputvoltage V1 is present between the first node O1 and ground. A secondoutput voltage V2 is present between the second node O2 and ground. Athird output voltage V3 is present between the third node O3 and ground.

A first comparator 12 compares the first output voltage V1 with a firstreference voltage VR1 to supply a first output signal. A secondcomparator 11 compares the second output voltage V2 with a secondreference voltage VR2 to supply a second output signal. A thirdcomparator 10 compares the third output voltage V3 with a thirdreference voltage VR3 to supply a third output signal.

Based on the first, second and third output signals, a logic circuit 13determines whether a number of the output voltages V1, V2, V3 which havea value above their associated reference voltage VR1, VR2, VR3, islarger than, smaller than, or equal to a number of the multitude ofoutput voltages V1, V2, V3 which have a value below their associatedreference voltage VR1, VR2, VR3. The cycle generator 14 will generate,in a sequence SE of cycles CY1, CY2, CY3 (see FIG. 4), a first number N1of cycles to which the minimum duty cycle D1 is allocated and a secondnumber N2 of cycles to which the maximum duty cycle D2 is allocatedcorresponding to the number of the output voltages V1, V2, V3 which havea value above their associated reference voltage VR1, VR2, VR3, largerthan, smaller than, or equal to a number of the multitude of outputvoltages V1, V2, V3 which have a value below their associated referencevoltage VR1, VR2, VR3. Thus, if the number of the output voltages V1,V2, V3 which have a value above their associated reference voltage VR1,VR2, VR3, is larger than a number of the multitude of output voltagesV1, V2, V3 which have a value below their associated reference voltageVR1, VR2, VR3, the first number N1 will be larger than the second numberN2.

The controller CO comprises the comparators 10, 11 and 12, the logiccircuit 13, and the cycle generator 14.

In another embodiment in accordance with the invention, as is shown inFIG. 3, the logic circuit 13 determines the number N1 of output voltagesV1, V2, V3 which have a value above their associated reference voltageVR1, VR2, VR3 and the number N2 of output voltages V1, V2, V3 which havea value below their associated reference voltage VR1, VR2, VR3.

Now, the cycle generator 14 receives the numbers N1 and N2 and suppliesthe switching signals CS0, CS1, CS2, and CS3 to the main switch S0, thefirst output switch S1, the second output switch S2, and the thirdoutput switch S3, respectively. The cycle generator 14 generates thecycles CY1, CY2, CY3 (see FIG. 4) either with the minimum duty cycle D1or the maximum duty cycle D2 which is larger than the minimum duty cycleD1 to obtain a first number N1 of cycles CY1, CY2, CY3 with the minimumduty cycle D1 and a second number N2 of cycles CY1, CY2, CY3 with themaximum duty cycle D2.

In a further embodiment in accordance with the invention, the cyclegenerator 14 comprises a sequencer 140 which controls an order of thecycles CY1, CY2, CY3 in a sequence SE such that, as much as possible atthe present values of the first number N1 and the second number N2, oneof the cycles CY1, CY2, CY3 with the maximum duty cycle D2 precedes oneof the cycles CY1, CY2, CY3 with the minimum duty cycle D1. In thismanner, first, during one of the cycles with the maximum duty cycle D2,the average value of the current IL through the inductor L increases,and then, during the successive cycle with the minimum duty cycle D1,the average value of the current IL through the inductor L decreases.Consequently, the chance that the current IL through the inductor Lbecomes zero is minimized.

Alternatively, the sequencer 140 may control the order of the cyclesCY1, CY2, CY3 in a sequence SE to first comprise all the cycles CY1,CY2, CY3 with the maximum duty cycle D2 and then all the cycles CY1,CY2, CY3 with the minimum duty cycle D1. Again, the chance that thecurrent IL through the inductor L becomes zero is The cycle generator 14may further comprise an allocator 141 which allocates the first numberN1 of the minimum duty cycles D1 as much as possible to cycles CY1, CY2,CY3 associated with output voltages V1, V2, V3 which have a value belowtheir associated reference voltage VR1, VR2, VR3, and the second numberN2 of the maximum duty cycles D2 as much as possible to cycles CY1, CY2,CY3 associated with output voltages V1, V2, V3 which have a value abovetheir associated reference voltage VR1, VR2, VR3. In cycles CY1, CY2,CY3 with the minimum duty cycle D1, the duration of the on-time TON ofthe output switch (one of the first, second, or third switches S1, S2,S3) is larger than in the cycles with the maximum duty cycle D2 and isthus a larger amount of energy supplied to the associated load L1, L2,L3. This is exactly what is required at an output O1, O2, O3 with anoutput voltage V1, V2, V3 below its reference value VR1, VR2, VR3. Inthe same manner, the maximum duty cycles D2 are allocated as much aspossible to cycles CY1, CY2, CY3 of which the associated output voltagesV1, V2, V3 have a value above their corresponding reference voltage VR1,VR2, VR3.

In another embodiment in accordance with the invention, the allocater(141) further allocates the minimum duty cycle D1 to cycles CY1, CY2,CY3 associated with output voltages V1, V2, V3 which have a value abovetheir associated reference voltage VR1, VR2, VR3 if the first number N1is larger than the number of output voltages V1, V2, V3 which have avalue below their associated reference voltage VR1, VR2, VR3. Or theother way around, the maximum duty cycle D2 is further allocated tocycles CY1, CY2, CY3 associated with output voltages V1, V2, V3 whichhave a value below their associated reference voltage VR1, VR2, VR3 ifthe second number N2 is larger than the number of output voltages V1,V2, V3 which have a value above their associated reference voltage VR1,VR2, VR3.

In yet another embodiment in accordance with the invention, theallocator 141 allocates a predetermined one of the cycles CY1, CY2, CY3in a sequence SE wherein a lowest amount of energy is transferred to oneof the output voltages V1, V2, V3 of which the value is above theassociated reference voltage VR1, VR2, VR3. This causes a minimalfurther increase of an output voltage V1, V2, V3 which has a valuealready higher than its reference value VR1, VR2, VR3. In the samemanner, the allocator 141 may allocate a predetermined one of the cyclesCY1, CY2, CY3 in a sequence SE wherein a highest amount of energy istransferred to one of the output voltages V1, V2, V3 of which the valueis below the associated reference voltage VR1, VR2, VR3.

The allocator 141 may allocate as the first cycle CY1 in a sequence SEan output voltage V1, V2, V3 of which the value is above the associatedreference voltage VR1, VR2, VR3 and to which a minimum duty cycle D1 isallocated. Usually, the first cycle CY1 in a sequence starts with thelowest average value of the current IL in the inductor L. This is due tothe fact that cycles CY1, CY2, CY3 with the minimum duty cycle D1 occurat the end of the sequence SE. This lowest amount of energy should besupplied to an output O1, O2, O3 which is going to receive a much largeramount of energy than required. This is particularly true for an outputO1, O2, O3 that already has a voltage V1, V2, V3 above its referencevalue VR1, VR2, VR3 and to which a minimum duty cycle D1 has to beallocated because there are no maximum duty cycles D2 left.

The allocator 141 may allocate, in a sequence SE, a last cycle CY1 towhich a maximum duty cycle D2 is allocated to an output voltage V1, V2,V3 of which the value is below the associated reference voltage VR1,VR2, VR3 and to which a maximum duty cycle D2 is allocated. Usually, ina sequence SE, the last cycle CY1, CY2, CY3 to which a maximum dutycycle D2 is allocated has the highest average value of the current IL inthe inductor L. This is due to the fact that cycles CY1, CY2, CY3 withthe minimum duty cycle D1 occur at the end of the sequence SE. Thishighest amount of energy should be supplied to an output O1, O2, O3which is going to receive a much smaller amount of energy than required.This is particularly true for an output O1, O2, O3 which has already avoltage V1, V2, V3 below its reference value VR1, VR2, VR3 and to whicha maximum duty cycle D2 has to be allocated because there are no minimumduty cycles D1 left.

The allocator 141 may, if in a preceding sequence SE, the minimum dutycycle D1 is allocated to a particular one of the output voltages V1, V2,V3 while the associated reference voltage VR1, VR2, VR3 is lower,allocate in a next sequence SE the maximum duty cycle D2 to thisparticular one of the output voltages V1, V2, V3. Or, similarly, theallocator 114 may, if in a preceding sequence SE the maximum duty cycleD2 is allocated to a particular one of the output voltages V1, V2, V3while the associated reference voltage VR1, VR2, VR3 is higher, allocatein a next sequence SE the minimum duty cycle D1 to this particular oneof the output voltages V1, V2, V3. Thus, if in a particular sequence SE,either the minimum D1 or the maximum D2 duty cycle has to be allocatedto an output O1, O2, O3 of which the voltage V1, V2, V3 is above orbelow its reference level VR1, VR2, VR3, respectively, in a nextsequence SE the correct duty cycle is allocated to this output O1, O2,O3. This has the advantage, that the wrong allocation of duty cycleswill be averaged over time and thus its negative influence on theregulation of the output voltages V1, V2, V3 concerned is minimized.

In a further embodiment in accordance with the invention, the DC-DCconverter further comprises mode detectors 15 which keep track of themodes of the outputs O1, O2, O3. The mode detectors, combined in theblock indicated by 15, determine the new mode of each of the outputs O1,O2, O3 based on the output signals of the comparators 10, 11, 12 and theprevious mode of the outputs O1, O2, O3, as is elucidated with respectto FIG. 6, to supply a control signal to a sequence controller 142 ofthe cycle generator 14. The sequence controller 142 controls a number ofcycles CY required in a sequence SE such that cycles CY are generatedonly for outputs O1, O2, O3 which are in a state indicating that currenthas to be supplied to the associated loads L1, L2, L3 and not foroutputs O1, O2, O3 which are in a state indicating that no current hasto be supplied to the associated loads L1, L2, L3.

FIG. 4 show signals for elucidating the operation of the DC-DC converterof FIG. 3. FIGS. 4A, 4B, 4C show the first, second and third outputvoltages V1, V2, V3 and their associated reference levels VR1, VR2 andVR3, respectively. FIG. 4D shows the current IL in the inductor L.

At the instant t15, as indicated by the arrows SV1, SV2, SV3 thecomparators 12, 11, 10 compare the output voltages V1, V2, V3 with thereference levels VR1, VR2, VR3, respectively. The output voltages V1 andV2 both have a value below their associated reference levels VR1 andVR2. The output voltage V3 has a value above its associated referencelevel VR3. Consequently, in the next sequence SE from instant t15 toinstant t21, two of the cycles CY1, CY2, CY3 will have the maximum dutycycle D2, and one of the cycles CY1, CY2, CY3 will have the minimum dutycycle D1.

The allocation of the one minimum duty cycle D1 and the two maximum dutycycles D2 in the sequence SE may be performed in several ways.Preferably, first, it is tried to allocate minimum duty cycles D1 tocycles CY1, CY2, CY3 in which the output voltage V1, V2, V3 is below theassociated reference voltage VR1, VR2, VR3, and to allocate maximum dutycycles D2 to cycles CY1, CY2, CY3 in which the output voltage V1, V2, V3is above the associated reference voltage VR1, VR2, VR3. Therefore, ifavailable, a maximum duty cycle D2 has to be allocated to the thirdswitch S3 because the third output voltage V3 is higher than itsreference level VR3, and a minimum duty cycle D1 has to be allocated tothe first and second switch S1 and S2.

However, in the embodiment in accordance with the invention as shown inFIG. 4D, to either the first V1 or the second V2 output voltage amaximum duty cycle D2 has to be allocated as there is only a singleminimum duty cycle D1 to be allocated. Thus in the process of allocatingthe single minimum duty cycle D1 and the two maximum duty cycles D2 tothe three available cycles CY1, CY2, CY3 in the sequence SE it has beendecided to allocate one of the maximum duty cycles D2 to the thirdswitch S3 (the third output voltage V3 has a value above its referenceVR1). The other maximum duty cycle D2 and the single minimum duty cycleD1 are allocated to the switches S1 and S2. For one of the switches S1,S2 this is correct because a minimum duty cycle D1 should be allocatedto output voltages V1 and V2 which have a value below their referencevalues VR1 and VR2. For the other one of the switches S1, S2 this isincorrect.

It is advantageous to select the allocation in time of the duty cyclesin the order: first the two maximum duty cycles D2 and then the minimumduty cycle D1. In this manner, first the average current IL through theinductor L increases preventing the current IL from crossing zero duringthe cycle in which the minimum duty cycle D1 occurs.

In a next step, it has to be selected in what order the power has to bedelivered to the outputs O1, O2, O3. It is clear that the switch S3should be operated with the maximum duty cycle D2, and thus should beassociated with the first or the second cycle CY1 or CY2. As the thirdoutput voltage V3 has already a value above its reference value VR3 itis advantageous to supply as little as possible power to the thirdoutput O3. Consequently, this third switch S3 should be associated withthe first cycle CY1 because the average current IL in the inductor L isminimal. The association of the first and the second switch S1, S2 tothe second and third cycle S2, S3 is not important, one of the switchesS2, S3 will be controlled correctly, the other will not. Preferably, ifpossible, in a next sequence SE, the allocation to the switches S2 andS3 is reversed to obtain an averaging effect.

In that which follows some embodiments in accordance with the inventionare elucidated in more detail. Discussed are: first a dual output DC-DCup-converter, secondly a triple output up-converter, thirdly dual outputdown-converter.

The dual output up-converter is described with reference to FIG. 3 fromthe third output O3 and the associated components S3, C3, L3 and 10 areomitted. For the dual output up-converter, with two outputs O1 and O2,there are four output load options:

-   -   both outputs O1 and O2 require a load current to flow into the        loads L1 and L2 to keep the output voltages V1 and V2 high        enough,    -   one output O1 requires a load current to flow in its associated        load L1,    -   the other output O2 requires a load current,    -   both outputs O1 and O2 do not require a load current flowing        into the loads L1 and L2 to prevent the output voltages V1 and        V2 from rising too high.

When no output load current is required at both outputs O1 and O2, theoutput voltages V1 and V2 of both outputs O1 and O2 will be above theirassociated reference values VR1 and VR2 and no next cycles CY arerequired as is shown in the next table. V1 V2 L1 L2 Nextcycles >VR1 >VR2 off off —

As soon as one of the output voltages V1 or V2 drops below itsassociated reference level VR1, VR2, the controller CO should switch tothe situation with one output requiring a load current. With a maximumof one output O1, O2 with load current, the principle works the same aswith single output control as is disclosed in WO 02/058220-A1. Thismeans that if the output voltage V1, V2 is below its reference valueVR1, VR2, the next switch cycle CY should have the maximum duty cycle,and when the output voltage V1, V2 is above its reference value VR1,VR2, the next switch cycle CY should be the minimum duty cycle D1. Thus,only the output O1, O2 with load current will get switching cycles CYand output power. The other output O1, O2 stays at a level above itsreference level VR1, VR2 and gets no switching cycles CY as is shown inthe following table, wherein the i in Dij refers to the minimum dutycycle if i=1 and to the maximum duty cycle if i=2, and wherein j refersto output O1 (voltage V1) ifj=1 and to output O2 (voltage V2) ifj=2. V1V2 L1 L2 Next cycles >VR1 >VR2 on off D1, 1 <VR1 >VR2 on off D2,1 >VR1 >VR2 off on D1, 2 >VR1 <VR2 off on D2, 2

As soon as the other output O1, O2 drops below its reference voltageVR1, VR2, the controller CO should switch to the two-output situation.When the load L1, L2 at the active output O1, O2 is switched off and theoutput voltage V1, V2 gets and stays above its reference value VR1, VR2,the controller CO should switch back to the no-load situation at bothoutputs O1, O2.

For two outputs O1, O2 with load current, the inductor current IL has tobe adapted correctly and the power has to be distributed according tothe need at the outputs O1 and O2. With two outputs O1, O2 there arefour options:

-   -   both outputs O1, O2 have an output voltage V1, V2 above their        reference level VR1, VR2,    -   the first output O1 has an output voltage V1 above its reference        level VR1 and the second output O2 has an output voltage V2        below its reference level VR2,    -   the first output O1 has an output voltage V1 below its reference        level VR1 and the second output O2 has an output voltage V2        above its reference level VR2,    -   both outputs O1, O2 have an output voltage V1, V2 below their        reference level VR1, VR2.

The inductor current IL should increase when both output voltages V1 andV2 have values below their reference value VR1, VR2. The inductorcurrent IL should decrease when both output voltages V1, V2 have valuesabove their reference value VR1, VR2. And, the inductor current IL hasto remain at the same level when one of the output voltages O1, O2 has avalue above its associated reference level VR1, VR2, and one of theoutput voltages O1, O2 has a value below its associated reference levelVR1, VR2. This results in a sequence SE of two maximum cycles D2 whenthe inductor current IL should increase, two minimum cycles D1 when theinductor current IL has to decrease, and one minimum D1 and one maximumD2 duty cycle when the inductor current IL must remain at the samelevel.

Thus, when both outputs O1, O2 have a voltage V1, V2 above theirreference level VR1, VR2, they will both get a minimum duty cycle D1. Inthe same way when both outputs have a voltage below their referencelevel VR1, VR2, they both will get a second duty cycle D2. When one ofthe outputs O1, O2 is above its reference level VR1, VR2, and one O1, O2below its reference level VR1, VR2, the situation is different. Sincethe maximum duty cycle D2 has a short second phase (during which theswitch S1, S2 arranged between the inductor and the load L1, L2 isclosed) the energy transfer to the output O1, O2 is smaller than duringthe minimum duty cycle D1 which has a longer second phase. This meansthat the output O1, O2 with an output voltage V1, V2 above its referencelevel VR1, VR2 will get a maximum duty cycle D2 and the output O1, O2with an output voltage V1, V2 below its reference level VR1, VR2 willget a minimum duty cycle D1. To maximize the output power and preventzero current in this situation first the maximum duty cycle D2 willoccur and then a minimum duty cycle D1.

The next table shows these control rules for two active outputs. Again,the i in Dij refers to the minimum duty cycle if i=1 and to the maximumduty cycle if i=2, and j refers to output O1 (voltage V1) ifj=1 and tooutput O2 (voltage V2) ifj=2. Each of the sequences comprises twosuccessive next cycles. V1 V2 L1 L2 Next cycles >VR1 >VR2 on on D1, 1;D1, 2 >VR1 <VR2 on on D2, 1; D1, 2 <VRl >VR2 on on D2, 2; D1, 1 <VR1<VR2 on on D2, 1; D2, 2

When the load L1, L2 at one of the outputs O1, O2 is switched off andthe output voltage V1, V2 gets and stays above its reference level VR1,VR2, the controller CO should switch back to the single outputsituation. When the load L1, L2 at both outputs O1, O2 is switched offand the output voltages V1, V2 get and stay above their reference levelsVR1, VR2, the controller CO should switch back to the no-load situation.

If, as shown in FIG. 3, the up-converter has three outputs O1, O2, O3,there are eight output load options:

-   -   all outputs O1, O2, O3 have load current,    -   two of the outputs O1, O2, O3 have load current, one of the        outputs O1, O2, O3 has not (3 options)    -   one of the outputs O1, O2, O3 has load current, two of the        outputs O1, O2, O3 have not (3 options)    -   all outputs O1, O2, O3 have no-load current.

With zero, one or two outputs O1, O2, O3 with load current the controlis performed as described above for the two-output controllers. Forthree outputs O1, O2, O3, the outcome of the output voltage measurementhas eight options:

-   -   all outputs O1, O2, O3 have a voltage V1, V2, V3 above their        reference level VR1, VR2, VR3,    -   two of the outputs O1, O2, O3 have a voltage V1, V2, V3 above        their reference level VR1, VR2, VR3 and one below its reference        level VR1, VR2, VR3 (3 options),    -   one of the outputs O1, O2, O3 has a voltage V1, V2, V3 above its        reference level VR1, VR2, VR3 and two below their reference        level VR1, VR2, VR3 (3 options),    -   all outputs O1, O2, O3 have a voltage V1, V2, V3 below their        reference level VR1, VR2, VR3.

When all outputs O1, O2, O3 are below their reference level VR1, VR2,VR3, the inductor current IL should have a large increase, which resultsin three maximum duty cycles D2, one for each output.

When all outputs O1, O2, O3 are above their reference level VR1, VR2,VR3, the inductor current IL should have a large decrease, which resultsin three minimum duty cycles D1, one for each output. When two of theoutputs O1, O2, O3 are above their reference level VR1, VR2, VR3 and oneoutput below its reference level VR1, VR2, VR3, the inductor current ILshould decrease, which results in one maximum duty cycle D2 and twominimum duty cycles D1, wherein the maximum duty cycle D2 is allocatedto one of the outputs O1, O2, O3 above its reference level VR1, VR2,VR3, and the first one of the minimum duty cycles D1 is allocated to oneof the outputs O1, O2, O3 below its reference level VR1, VR2, VR3 sincethis cycle has the highest energy transfer due to the higher inductorcurrent IL.

When one of the outputs O1, O2, O3 is above its reference level VR1,VR2, VR3 and two of the outputs O1, O2, O3 are below their referencelevel VR1, VR2, VR3, the inductor current IL should increase, whichresults in two maximum duty cycles D2 and one minimum duty cycle D1,wherein the minimum duty cycle D1 is allocated to one of the outputs O1,O2, O3 below their reference level VR1, VR2, VR3, and the second maximumduty cycle D2 is allocated to the other one of the outputs O1, O2, O3with a value below its reference level VR1, VR2, VR3 since this cyclehas the highest energy transfer due to the higher inductor current (IL).The control rules for three active outputs are shown in the table below.The i in Dij refers to the minimum duty cycle if i=1 and to the maximumduty cycle if i=2, and wherein j refers to output O1 (voltage V1) ifj=1,to output O2 (voltage V2) ifj=2, and to output O3 (voltage V3) if j=3.Each of the sequences comprises three successive next cycles. V1 V2 V3L1 L2 L3 Next cycles >VR1 >VR2 >VR3 on on on D1, 1; D1, 2; D1, 3<VR1 >VR2 >VR3 on on on D2, 2; D1, 1; D1, 3 >VR1 <VR2 >VR3 on on on D2,3; D1, 2; D1, 1 >VR1 >VR2 <VR3 on on on D2, 1; D1, 3; D1, 2 >VR1 <VR2<VR3 on on on D2, 1; D2, 2; D1, 3 <VR1 >VR2 <VR3 on on on D2, 2; D2, 3;D1, 1 <VR1 <VR2 >VR3 on on on D2, 3; D2, 1; D1, 2 <VR1 <VR2 <VR3 on onon D2, 1; D2, 2; D2, 3

When the load L1, L2, L3 at one or two of the outputs O1, O2, O3 isswitched off and the output voltage V1, V2, V3 gets and stays above itsreference value VR1, VR2, VR3, the controller CO should switch back tothe dual or single output situation. When the load L1, L2, L3 at alloutputs O1, O2, O3 is switched off and the output voltages V1, V2, V3get and stay above their reference values VR1, VR2, VR3 the controllerCO should switch back to the no-load situation.

For a down-converter, the situation is different. In down-conversion theinductor current IL flows to the output O1, O2, O3 during the completeswitch cycle CY and not only during the second phase. This means thatenergy is transferred during the complete switch cycle CY, which resultsin no significant difference in energy transfer between a minimum D1 anda maximum D2 duty cycle. Similar to up-conversion the different optionsfor two outputs O1 and O2 will be elucidated below.

With no output load current at both outputs O1, O2, the output voltageV1, V2 of both outputs O1, O2 will be above their reference level VR1,VR2 as is shown in the next table and no cycles will be required. V1 V2L1 L2 Next cycles >VR1 >VR2 off Off —

With at maximum one of the outputs O1, O2 with load current, theprinciple works identical by with single output control describedearlier. This means that if the output voltage V1, V2 is below itsreference level VR1, VR2, the next switch cycle CY should have a maximumduty cycle D2, and when the output voltage V1, V2 is above its referencelevel VR1, VR2, the next switch cycle CY should have a minimum dutycycle D1. Only the output O1, O2 with load current will get a switchingcycle CY and output power. The other output O1, O2 stays at a levelabove its reference level VR1, VR2 and gets no switching cycles CY. Thenext table lists the control rules for one active output. V1 V2 L1 L2Next cycles >VR1 >VR2 on off D1, 1 <VR1 >VR2 on off D2, 1 >VR1 >VR2 offon D1, 2 >VR1 <VR2 off on D2, 2

For two outputs O1, O2 with load current the inductor current IL has tobe adapted correctly and the power has to be distributed according tothe need at the output O1, O2. The main difference with up-conversion isthat energy is transferred during the complete switching cycle CY.Consequently, the amount of energy transferred does not depend on theduty cycle, thus, the choice of the minimum D1 and the maximum D2 dutycycle is less critical. The table below shows the control rules for twoactive outputs, always two cycles CY occur during a sequence SE. V1 V2L1 L2 Next cycles >VR1 >VR2 on on D1, 1 D1, 2 >VR1 <VR2 on on D2, 2 D1,1 or D2, 1 D1, 2 <VR1 >VR2 on on D2, 1 D1, 2 or D2, 2 D1, 1 <VR1 <VR2 onon D2, 1 D2, 2

The conclusion for down-conversion is that at least the same rules arevalid as for up-conversion. There are additional alternatives since thechoice from the minimum D1 and the maximum D2 duty cycles is no longercritical for the outputs O1, O2 but is only relevant for the inductorcurrent IL.

FIG. 5 shows a block diagram of an apparatus with a DC-DC converter inaccordance with the invention. The DC-DC converter in accordance withthe invention, which is denoted by 100, receives an input voltage Vinand supplies a first output voltage V1 to a first circuit 101, a secondoutput voltage V2 to a second circuit 102, and a third output voltage V3to a third circuit 103. The first, second and third circuits 101, 102,103 may be internal circuits (for example a receiver, a transmitter anda display in a mobile phone, or signal processing circuits and a displayin a television or computer display) in an audio-visual application ormay be external apparatuses.

FIG. 6 shows a state diagram for elucidating the modes of outputvoltages. For the control of the converter, it is not required tomeasure whether an output Oi requires a load current or not. The mode ofan output Oi is tracked with an algorithm elucidated with respect to thestate diagram. The index i is an integer which indicates one of aplurality of outputs, depending on how many output Oi the converter has.

The modes are defined as follows:

-   -   mode 0: the output voltage Vi is larger than its reference        voltage VRi, no power required, the output Oi is not active,    -   mode 1: the output voltage Vi is larger than its reference        voltage VRi, minimum power required, the output Oi is active,    -   mode 2: the output voltage Vi is smaller than its reference        voltage VRi, maximum power required, the output Oi is active,

The value of the mode is determined by the previous mode and the newsampled output voltage Vi. If the sampled output voltage Vi is smallerthan its reference value VRi, always mode 2 will be reached. If thesampled output voltage Vi is larger than its reference value VRi, mode 2changes into mode 1, and mode 1 changes into mode 0. If the outputvoltage Vi is larger than its reference value VRi, the mode 1 willbecome mode 0 and mode 0 will stay mode 0 and the output Oi is notactive. Thus, in active operation, for each output Oi, the mode willalternate between mode 1 and mode 2 in a sequence that depends on themeasured value of the output voltage Vi. If one of the outputs Oi haszero load its output voltage Vi will remain above its reference levelVRi which results in mode 0.

FIG. 7 shows a flow chart of a control algorithm in a DC-DC converter inaccordance with the invention. The flow chart elucidates the operationof a dual output up-converter.

In step 100 the values of the output voltages V1 and V2 are measured.

In step 101 there is checked whether both the value of the outputvoltage V1 is smaller than its reference value VR1 and the value of theoutput voltage V2 is smaller than its reference value VR2. If they are,in step 102, both the mode of output O1 (at which the voltage V1 ispresent) and output O2 (at which the voltage V2 is present) will changeinto mode 2, if the mode was 2 it will stay 2. And in step 103, in asequence SE of cycles CY, the first maximum duty cycle D2 is applied tothe first switch S1 associated with the first output voltage V1, andthen the second maximum duty cycle D2 is applied to the second switch S2associated with the second output voltage V2, or the other way around.

If they are not, in step 104 there will be checked whether both thevalue of the output voltage V1 is larger than its reference value VR1and the value of the output voltage V2 is smaller than its referencevalue VR2. If they are, in step 105 there will be checked whether themode of output O1 is lower than mode 2. If it is, in step 106, the modeof output 1 will be changed into mode 0, and the mode of output 2 willbecome mode 2, and only a maximum duty cycle D2 will be applied to theswitch S2. No switching cycle will be allocated to the switch S1. If themode of output O1 is not lower than 2, in step 108, the mode of outputO1 will become 1, and the mode of output 2 will be 2, and first amaximum duty cycle D2 will be applied to the first switch S1, and then aminimum duty cycle D1 will be applied to the second switch S2.

If the outcome of step 104 is no, In step 110 there will be checkedwhether the value of the output voltage V1 is smaller than its referencevalue VR1 and whether the value of the output voltage V2 is larger thanits reference value VR2. If they are, in step 111 there will be checkedwhether the mode of the output O2 is smaller than 2, if it is, in step112, the mode of output O1 will be changed into mode 2, and the mode ofoutput O2 will be mode 0, and only a maximum duty cycle D2 will beapplied to the switch S1. No switching cycle will be allocated to theswitch S2. If the mode of the output O2 is not lower than 2, in step114, the mode of output O1 will be mode 2 and the mode of output O2 willbe mode 1, and first a maximum duty cycle D2 will be applied to thesecond switch S2 and then a minimum duty cycle will be applied to thefirst switch S1.

If step 116 is reached, the value of the output voltage V1 will belarger than its reference value VR1 and the value of the output voltageV2 will be larger than its reference value VR2. In step 117 is detectedwhether both the mode of the first output O1 and of the second output O2is lower than mode 2. If it is, in step 119, the mode of outputs O1 andO2 will become mode 0, and in step 119 a wait cycle will be starteduntil at least one of the output voltages V1, V2 drops below itsreference value VR1, VR2. If not then step 120 will be performed.

In step 120 there is checked whether the output O1 has a mode smallerthan mode 2, if it has, in step 121, the mode of output O1 will be mademode 0, and the mode of output O2 will be made mode 1, and in step 122the sequence SE will contain a single minimal duty cycle D1 applied tothe switch S2. If it has not then step 123 will be performed.

In step 123 is checked whether the output O2 has a mode smaller thanmode 2, if it has, in step 124, the mode of output O1 will be made mode1, and the mode of output O2 will be made mode 0, and in step 125 thesequence SE will contain a single minimal duty cycle D1 applied to theswitch S1. If the output O2 has a mode 2, in step 126 the mode ofoutputs O1 and O2 will become 1, and in step 127, the sequence SE willcomprise a minimal duty cycle D1 applied to the first switch S1 and aminimum duty cycle D1 applied to the second switch S2.

It should be noted that the above-mentioned embodiments illustraterather than limit the invention, and that those skilled in the art willbe able to design many alternative embodiments without departing fromthe scope of the appended claims.

In the claims, any reference signs placed between parentheses shall notbe construed as limiting the claim. The word “comprising” does notexclude the presence of elements or steps other than those listed in aclaim. The invention can be implemented by means of hardware comprisingseveral distinct elements, and by means of a suitably programmedcomputer. In the device claim enumerating several means, several ofthese means can be embodied by one and the same item of hardware. Themere fact that certain measures are recited in mutually differentdependent claims does not indicate that a combination of these measurescannot be used to advantage.

1. A multi-output DC-DC converter comprising: an inductor (L), a mainswitch (S0) for periodically coupling a DC-input voltage (Vin) to theinductor (L), a multitude of output switches (S1, S2, S3) coupled to theinductor (L), each one for generating an associated one of a multitudeof output voltages (V1, V2, V3) to an associated one of a multitude ofloads (L1, L2, L3), and a controller (1) for controlling the main switch(S0) and the output switches (S1, S2, S3) in a sequence (SE) of cycles(CY1, CY2, CY3), each one of the cycles (CY1, CY2, CY3) comprising anon-phase (TO1, TO2, TO3) of the main switch (S0) followed by an on-phase(T1, T2, T3) of one of the multitude of the output switches (S1, S2,S3), the controller (1) comprising: a multitude of comparators (10, 11,12) each one for comparing an associated one of the multitude of outputvoltages (V1, V2, V3) with an associated one of a multitude of referencevoltages (VR1, VR2, VR3), means for determining (13) whether a number ofthe output voltages (V1, V2, V3) which have a value above theirassociated reference voltage (VR1, VR2, VR3) is larger than, smallerthan, or equal to a number of the multitude of output voltages (V1, V2,V3) which have a value below their associated reference voltage (VR1,VR2, VR3), means for generating (14) the cycles (CY1, CY2, CY3) eitherwith a first duty cycle (D1) or a second duty cycle (D2) being largerthan the first duty cycle (D1) to obtain a first number (N1) of cycles(CY1, CY2, CY3) with the first duty cycle (D1) and a second number (N2)of cycles (CY1, CY2, CY3) with the second duty cycle (D2), the firstnumber (N1) being larger than, smaller than, or equal to the secondnumber (N2), respectively.
 2. A multi-output DC-DC converter as claimedin claim 1, wherein the first number (N1) is equal to the number ofoutput voltages (V1, V2, V3) which have a value above their associatedreference voltage (VR1, VR2, VR3), and wherein the second number (N2) isequal to the number of output voltages (V1, V2, V3) which have a valuebelow their associated reference voltage (VR1, VR2, VR3).
 3. Amulti-output DC-DC converter as claimed in claim 2, wherein the meansfor generating (14) the cycles comprises a sequencer (140) forcontrolling an order of the cycles (CY1, CY2, CY3) in a sequence (SE)wherein, as much as possible at the present values of the first number(N1) and the second number (N2), one of the cycles (CY1, CY2, CY3) withthe second duty cycle (D2) precedes one of the cycles (CY1, CY2, CY3)with the first duty cycle (D1).
 4. A multi-output DC-DC converter asclaimed in claim 2, wherein the means for generating (14) the cyclescomprises a sequencer (140) for controlling an order of the cycles (CY1,CY2, CY3) in a sequence (SE) to first comprise all the cycles (CY1, CY2,CY3) with the second duty cycle D2) and then all the cycles (CY1, CY2,CY3) with the first duty cycle (D1).
 5. A multi-output DC-DC converteras claimed in claim 2, wherein the means for generating (14) the cyclescomprises a means for allocating (141): the first number (N1) of thefirst duty cycles (D1) as much as possible to cycles (CY1, CY2, CY3)associated with output voltages (V1, V2, V3) that have a value belowtheir corresponding reference voltage (VR1, VR2, VR3), and the secondnumber (N2) of the second duty cycles (D2) as much as possible to cycles(CY1, CY2, CY3) associated with output voltages (V1, V2, V3) which havea value above their corresponding reference voltage (VR1, VR2, VR3). 6.A multi-output DC-DC converter as claimed in claim 5, wherein the meansfor allocating (141) the number of duty cycles is adapted for furtherallocating the first duty cycle (D1) to cycles (CY1, CY2, CY3)associated with output voltages (V1, V2, V3) that have a value abovetheir corresponding reference voltage (VR1, VR2, VR3) if the firstnumber (N1) is larger than the number of output voltages (V1, V2, V3)that have a value below their associated reference voltage (VR1, VR2,VR3).
 7. A multi-output DC-DC converter as claimed in claim 5, whereinthe means for allocating (141) is adapted for further allocating thesecond duty cycle (D2) to cycles (CY1, CY2, CY3) associated with outputvoltages (V1, V2, V3) that have a value below their associated referencevoltage (VR1, VR2, VR3) if the second number (N2) is larger than thenumber of output voltages (V1, V2, V3) that have a value above theirassociated reference voltage (VR1, VR2, VR3).
 8. A multi-output DC-DCconverter as claimed in claim 5, wherein the means for allocating (141)is adapted for allocating to a predetermined one of the cycles (CY1,CY2, CY3) in a sequence (SE) wherein a lowest amount of energy istransferred to one of the output voltages (V1, V2, V3) of which thevalue is above the associated reference voltage (VR1, VR2, VR3).
 9. Amulti-output DC-DC converter as claimed in claim 5, wherein the meansfor allocating (141) is adapted for allocating as a first one of thecycle (CY1, CY2, CY3) in a sequence (SE) an output voltage (V1, V2, V3)of which the value is above the associated reference voltage (VR1, VR2,VR3) and to which a first duty cycle (D1) is allocated.
 10. Amulti-output DC-DC converter as claimed in claim 5, wherein the meansfor allocating (141) is adapted for allocating to a predetermined one ofthe cycles (CY1, CY2, CY3) in a sequence (SE) wherein a highest amountof energy is transferred to one of the output voltages (V1, V2, V3) ofwhich the value is below the associated reference voltage (VR1, VR2,VR3).
 11. A multi-output DC-DC converter as claimed in claim 5, whereinthe means for allocating (141) is adapted for allocating, in a sequence(SE), a last cycle (CY1) to which a second duty cycle is allocated to anoutput voltage (V1, V2, V3) of which the value is below the associatedreference voltage (VR1, VR2, VR3) and to which a second duty cycle (D2)is allocated.
 12. A multi-output DC-DC converter as claimed in claim 5,wherein the means for allocating (141) is adapted to allocate in a nextsequence (SE) the second duty cycle (12) to a particular one of theoutput voltages (V1, V2, V3), if in a preceding sequence (SE) the firstduty cycle (D1) is allocated to this particular one of the outputvoltages (V1, V2, V3) while the associated reference voltage (VR1, VR2,VR3) is lower.
 13. A multi-output DC-DC converter as claimed in claim 5,wherein the means for allocating (141) is adapted to allocate in a nextsequence (SE) the first duty cycle (D1) to a particular one of theoutput voltages (V1, V2, V3), if in a preceding sequence (SE) the secondduty cycle (D2) is allocated to this particular one of the outputvoltages (V1, V2, V3) while the associated reference voltage (VR1, VR2,VR3) is higher.
 14. A multi-output DC-DC converter as claimed in 1, themulti-output DC-DC converter further comprising mode detectors (15),each one being associated with one of the multiple output voltages (V1,V2, V3) for keeping track of a mode of each one of a multiple outputs(O1, O2, O3), each mode detector having three states (0, 1, 2), a firststate (0) indicating whether no load current is drawn from theassociated output (O1, O2, O3), a second state (1) and a third state (2)wherein load current is drawn from the associated output (O1, O2, O3),if the associated output (O1, O2, O3) is in the first state (0) and theassociated output voltage (V1, V2, V3) is smaller than its associatedreference voltage (VR1, VR2, VR3) the third state (2) is entered, if theassociated output (O1, O2, O3) is in the first state (0) and theassociated output voltage (V1, V2, V3) is larger than its associatedreference voltage (VR1, VR2, VR3) the first state (0) will bemaintained, if the associated output (O1, O2, O3) is in the second state(1) and the associated output voltage (V1, V2, V3) is larger than itsassociated reference voltage (VR1, VR2, VR3) the first state (0) isentered, if the associated output (O1, O2, O3) is in the second state(1) and the associated output voltage (V1, V2, V3) is smaller than itsassociated reference voltage (VR1, VR2, VR3) the third state (2) isentered, if the associated output (O1, O2, O3) is in the third state (2)and the associated output voltage (V1, V2, V3) is smaller than itsassociated reference voltage (VR1, VR2, VR3) the third state (2) ismaintained, if the associated output (O1, O2, O3) is in the third (2)state and the associated output voltage (V1, V2, V3) is larger than itsassociated reference voltage (VR1, VR2, VR3) the second state (1) isentered.
 15. A multi-output DC-DC converter as claimed in 14, the means(14) for generating the cycles further comprising a sequence controller(142) for controlling a number of cycles (CY) required in a sequence(SE) such that cycles (CY) are generated only for outputs (O1, O2, O3)that are in the second state (1) or the third state (2).
 16. Anapparatus comprising the multi-output DC-DC converter as claimed inclaim
 1. 17. A method of controlling a multi-output DC-DC convertercomprising: an inductor (L), a main switch (S0) for periodicallycoupling a DC-input voltage (Vin) to the inductor (L), a multitude ofoutput switches (S1, S2, S3) coupled to the inductor (L), each one forsupplying an associated one of a multitude of output voltages (V1, V2,V3) to an associated one of a multitude of loads (L1, L2, L3), themethod comprising: controlling (1) the main switch (S0) and the outputswitches (S1, S2, S3) in a sequence (SE) of cycles (CY1, CY2, CY3), eachone of the cycles (CY1, CY2, CY3) containing an on-phase (TO1, TO2, TO3)of the main switch (S0) followed by an on-phase (T1, T2, T3) of one ofthe multitude of the output switches (S1, S2, S3), the controlling (1)comprising: comparing (10, 11, 12) a corresponding one of the multitudeof output voltages (V1, V2, V3) with an associated one of a multitude ofreference voltages (VR1, VR2, VR3), determining (13) whether a number ofthe output voltages (V1, V2, V3) that have a value above theirassociated reference voltage (VR1, VR2, VR3), is larger than, smallerthan, or equal to a number of the multitude of output voltages (V1, V2,V3) that have a value below their associated reference voltage (VR1,VR2, VR3), means for generating (14) the cycles (CY1, CY2, CY3) eitheronly with a first duty cycle (D1 or a second duty cycle (D2) beinglarger than the first duty cycle (D1) to obtain a first number (N1) ofcycles (CY1, CY2, CY3) with the first duty cycle (D1) and a secondnumber (N2) of cycles (CY1, CY2, CY3) with the second duty cycle (D2),the first number (N1) being larger than, smaller than, or equal to thesecond number (N2), respectively.